Via connector and method of making same

ABSTRACT

An insulator substrate or printed circuit board (PCB) having a filled and plated via. A sidewall of the via and preferably opposite sides of the insulator substrate are first plated with a conductive material. The plated via is then filled with an electrically conductive fill composition. A conductive cap layer is preferably formed over both ends of the conductive fill composition and the opposite surfaces of the insulator substrate, and can be bonded to a surface mount contact as a land or a pad.

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This is a continuation of U.S. Ser. No. 09/840,251, filed Apr.23, 2001, now U.S. Pat. No. 6,598,291, issued Jul. 29, 2003; which is acontinuation-in-part of U.S. Ser. No. 09/045,615, filed Mar. 20, 1998,now abandoned, the entire disclosure of which is incorporated herein byreference.

FIELD OF THE INVENTION

[0002] The present invention relates in general to printed circuitboards and to methods for fabricating printed circuit boards. Moreparticularly, the present invention relates to printed circuit boardswith improved vias which provide electrical communication between wiringpatterns formed on two opposing surfaces of a circuit board and/orwithin the internal strata of the circuit board, and to methods formaking improved circuit boards having such vias.

BACKGROUND OF THE INVENTION

[0003] Increasing levels of integration of integrated circuit (IC) chipsreduces the chip count of a functional circuit, while significantlyincreasing the input/output (I/O) count of the individual integratedcircuits making up the functional circuit. This drive for increasedcircuit and component density in the individual IC chips leads to aparallel drive for increased circuit and component density in theprinted circuit boards carrying the chips and in the assemblies usingthem.

[0004] Typically, a conventional printed wiring board carries ICs aswell as other discrete electronic components and circuit elements, whichare interconnected to provide the particular electronic circuitfunctions. In the prior art, those ICs, discrete electronic components,and circuit elements are usually bonded to the printed wiring boardusing vias or through holes formed in the printed wiring board throughwhich lead wires may be inserted and soldered to the board. However,there have been advances in surface mounting technology widely employedin the printed wiring board manufacturing field. This technology permitsan IC to be mounted together with its associated elements on the printedwiring board without forming any through holes or vias in the board.Thus, ICs and other on-chip elements may be mounted on a surface mountland or chip land directly without using the through holes or vias.

[0005] To provide for the interconnections between the on-chip elementson the surface mount land on one side and a circuit on the opposite sideof, or within, the printed wiring board, the appropriate vias are oftenprovided remotely from the surface mount land, and any wiring patternrequired for interconnecting the elements by way of the vias must beformed on the surface of the base plate.

[0006] Thus, according to the prior art, the surface mount land or chipland and the vias or through holes are provided at different locationson the printed wiring board. As the size of each of the ICs and otherelements is reduced, a corresponding reduction in the size of thesurface mount land is required so that required board space isminimized. The wiring pattern that includes leads drawn out from thesurface mount land and distributed across different locations must beaccordingly fine, but technically, this is practically difficult toachieve. It is also difficult to secure the space required for wiringthe leads. In particular, for double-sided high-density wiring patternimplementation, this space limitation poses a problem.

[0007] The vias formed in the printed wiring board are exposed on eachof the opposite sides of the board. When leads are inserted through thecorresponding vias, and the associated circuit components are fixed bythe board in solder, surplus solder may flow through the vias, therebyreaching the components on the surface mount land.

[0008] In other conventional circuit boards which carry wiring patternsformed on two opposing major surfaces, vias or through holes are formedat desired positions after conductive layers are formed on the entiresurface of the opposing major surfaces of the circuit board. Innersurfaces of the thus formed vias are coated with plated layers throughthe use of a chemical plating method or a chemical/electrical platingmethod, thereby providing electrical communication between theconductive layers formed on the two major surfaces or internal to thecircuit board by way of the plated layers.

[0009] The vias are formed through the use of a drilling method or apunching method. Therefore, there is the possibility that the circuitboard or the conductive layers become distorted during the formation ofthe through holes. The thus formed distortion will adversely influencethe formation of the plated layers so that an effective electricalconnection cannot be achieved between the two conductive layers. Inaddition, fine wiring patterns cannot be formed near the vias due to thedistortion of the conductive layers. Thereafter, the conductive layersare shaped in a desired configuration to obtain wiring. patterns formedon both of the major surfaces of the circuit board.

[0010] Another example of prior art via connectors is disclosed in U.S.Pat. No. 3,601,523 “THROUGH HOLE CONNECTORS” to Arndt, issued on Aug.24, 1971, wherein a conductive adhesive is disposed in the through holesor vias for providing electrical communication between the conductivelayers formed on both of the major surfaces of the circuit board. In thedevice of the '523 patent, the vias are formed after the conductivelayers are formed on both of the major surfaces of the circuit boardand, therefore, there is a possibility that the conductive layers willbecome distorted near the vias. Moreover, in the '523 patent, electricalcommunication between the conductive layer and the conductive adhesiveis achieved only through the use of the thickness of the conductivelayer. In addition, the conductive adhesive is exposed to the ambience.Therefore, the shaping of the wiring patterns must be conducted throughthe use of a dry film or a resist sheet.

[0011] The increased circuit and component density in the printedcircuit boards makes the ability to locate either solder surface mountcomponents or place additional circuitry layers directly aboveconductive vias highly desirable. This is especially the case when thedensity of the vias required to service the I/0's of the surface mountcomponents is such that there is no surface area available forattachment pads interstitial to the through hole grid.

[0012] The problem is especially severe with fine pitch ball grid arraycomponents and flip chip attach integrated circuits. Soldering of thesesurface mount components to the surface pads, i.e., lands, ofconventional vias is highly undesirable. This is because the solder usedfor assembly tends to wick down into the vias. The result is low volume,unreliable solder joints.

[0013] One solution that has been proposed is filling the vias. However,known methods of filling vias of printed circuit boards havedeficiencies. For example, they suffer from bleed of the resin componentof the fill material along the surface of the boards. This resin alsobleeds into the holes which are not to be filled. This leads to shortcircuits and to soldering defects during assembly..

[0014] Thus, conductive vias provide an immediate connection from asurface mounted device to the core of a printed circuit board, therebyavoiding inefficient fan out routing patterns that consume space on theouter layers of the multilayer board. These designs, however, presentsignificant assembly problems. Small vias act as entrapment sites formaterials that can eventually re-deposit onto the host surface mountland and cause both assembly and reliability problems. Also, these viasact as unintended reservoirs for solder paste that is stenciled onto thesurface mount land and used to attached an electronic device to theboard. Consequently, an allowance must be made of the solder paste thatwill be captured by the via and will not be available for the solderjoint formed between the device and the board. Typically, the sameallowance is made for each via by slightly enlarging the solder pastestencil aperture for each surface mount pad containing a via by somecommon amount. Because the precise allowance needed varies from via tovia, this method leads to an insufficient amount of paste for some landscausing poor solder joints and an over-abundance of solder on otherscausing solder shorts; both of which unfavorably impact assembly yields.

[0015] Another example of prior art via connectors is disclosed in U.S.Pat. No. 5,557,844 “METHOD OF PREPARING A PRINTED CIRCUIT BOARD” toBhatt et al., issued on Sep. 24, 1996 and assigned to IBM, (referred toherein as “IBM”), wherein a printed circuit board has two types ofplated through holes, filled and unfilled. The two types of throughholes are formed at different times during the manufacturing process.The through holes that are to be filled are formed first, and thethrough holes that remain unfilled are later formed using the locationof the first through holes for registration. Because all the holes arenot formed simultaneously, misregistration of subsequently appliedwiring patterns with the holes is likely as a result of tolerancebuild-ups. Moreover, IBM uses an electroless deposition for the platingof the sidewalls of the through holes, thus limiting the layer thicknessto approximately 0.2 mils.

[0016] Although the art of vias and through hole connectors on printedcircuit boards is well developed, there remain some problems inherent inthis technology, particularly the vias and through hole connectorsacting as solder reservoirs, thus leading to soldering defects, and theelectrical conductivity of the vias. Therefore, a need exists for a viaor through hole connector that overcomes the drawbacks of the prior art.

SUMMARY OF THE INVENTION

[0017] According to one aspect of the present invention, a method ofpreparing a printed circuit board (PCB) comprises the steps of forming ahole in a substrate to form a via having a sidewall extendingtherethrough, depositing a first conductive material on opposite sidesof the substrate and on the sidewall of the via, filling the via with asecond conductive material to plug the via such that the via has noopening extending completely therethrough in a direction generallyperpendicular to the opposite sides of the substrate, and depositing athird conductive material on the first conductive material and on endsof the second conductive material in the via.

[0018] According to another aspect of the present invention, a method ofmaking a conductive via in an insulator circuit board substrate adaptedto carry wiring patterns on at least a first surface and a secondsurface thereof comprises the steps of providing an insulator substrate,forming a via having a sidewall in the insulator substrate between thefirst surface and the second surface by penetrating the insulatorsubstrate, depositing a first conductive layer on the first surface andon the sidewall of the via such that the first conductive layersubstantially covers the first surface of the insulator substrate andthe sidewall of the via while leaving an opening in the via, depositinga conductive material in the opening of the via to plug the via suchthat the opening does not extend completely through the via in adirection generally perpendicular to the first and second surfaces, andforming a second conductive layer on the first surface of the insulatorsubstrate subsequent to the forming of the via, the depositing of thefirst conductive layer, and the depositing of the conductive material inthe opening such that the second conductive layer forms a substantiallyflat surface extending across substantially all of the first conductivelayer and across an end portion of the conductive material in the via sothat the end portion is covered by and makes direct contact with thesecond conductive layer.

[0019] According to still another aspect of the present invention, amethod of preparing a printed circuit board (PCB) comprises the steps offorming a hole on at least one side of a substrate to form a via havinga sidewall extending at least partially through the substrate to aninternal surface of the substrate, depositing a first conductivematerial on the one side of the substrate and on the sidewall of the viasuch that the via has an opening, masking the substrate with a stencil,filling the opening with a second conductive material by moving thesecond conductive material through an opening in the stencil to plug thevia such that the opening in the via does not extend completely throughthe via in a direction generally perpendicular to the one side of thesubstrate, and depositing a third conductive material on the firstconductive material and on an end of the second conductive material inthe opening.

[0020] According to yet another aspect of the present invention, amethod of preparing a printed circuit board (PCB) comprises the steps offorming a plurality of holes on at least a first surface of a substrateto form a plurality of vias having sidewalls extending at leastpartially through the substrate to a second surface of the substrate,depositing a first conductive material on at least the first surface ofthe substrate and on the sidewalls of the vias such that. each of thevias has an associated opening, masking the substrate with a stencil toselectively cover a first predetermined number of the vias and reveal asecond predetermined number of the vias, filling the openings associatedwith the revealed vias with a second conductive material, and depositinga third conductive material on the first conductive material and on endsof the second conductive material in the filled openings.

[0021] According to a further aspect of the present invention, a circuitboard comprises a substrate having at least first and second generallyparallel surfaces and a via having a sidewall extending at leastpartially through the substrate from the first surface to the secondsurface. A first conductive layer extends over substantially all of thefirst surface and the via sidewall. A conductive material is positionedwithin the via and surrounded by the first conductive layer extendingover the via sidewall. This conductive material plugs the via such thatthe via has no opening extending from the first surface to the secondsurface. A second conductive layer extends over substantially all of thefirst conductive layer on the first surface, and over an end portion ofthe conductive material positioned within the via

[0022] According to still a further aspect of the present invention, acircuit board comprises a substrate having at least first and secondgenerally parallel surfaces and a via having a sidewall extendingthrough the substrate from the first surface to the second surface. Afirst conductive layer extends over substantially all of the firstsurface, the second surface, and the via sidewall. A conductive materialis positioned within the via and surrounded by the first conductivelayer extending over the via sidewall. This conductive material plugsthe via such that the via has no opening extending from the firstsurface to the second surface. A second conductive layer extends oversubstantially all of the first conductive layer on the first surface,and over a first end portion of the conductive material positionedwithin the via. A third conductive layer extends over substantially allof the first conductive layer on the second surface, and over a secondend portion of the conductive material positioned within the via.

[0023] Other aspects and features of the present invention will be inpart apparent and in part pointed out hereinafter.

BRIEF DESCRIPTION OF THE DRAWING

[0024]FIGS. 1A through 1E are sectional views of a circuit boardsubstrate and illustrate the fabrication steps of an exemplary viaconnector in accordance with the present invention.

[0025]FIG. 2 is a schematic representation showing a surface mount landin plan.

[0026] Corresponding reference characters indicate correspondingfeatures throughout the several views of the drawings.

DESCRIPTION OF EXEMPLARY EMBODIMENTS AND BEST MODE

[0027] According to the present invention, an insulator substrate orprinted circuit board (PCB) having a filled and plated via is provided.The plated via is filled with an electrically conductive fillcomposition. A conductive cap layer is formed atop the ends of thefilled via and can be bonded to a surface mount contact as a land or apad.

[0028]FIGS. 1A through 1E show fabrication steps of one embodiment ofthe via connector in accordance with the present invention.

[0029]FIG. 1A shows an insulator substrate 12, such as a printed circuitboard or a flexible thin-film substrate. Preferably, the substrate 12comprises a resin material (in contrast to, for example, ceramicmaterials), and even more preferably comprises a glass-filled resinmatetrial. Some typical glass-filled resin materials suitable for use inthe present invention include fiberglass reinforced epoxy resins (e.g.,FR4), cyanate ester (e.g., as used in the Gore Speed Board availablefrom Gore Corporation), polyphenylene ether (e.g., as used in theGigavar brand laminate available from Allied Signal), andepoxy/polyphenylene oxide (e.g., as used in the Getek brand laminateavailable from General Electric).

[0030] A through hole or via 10 is formed in the insulator substrate 12at a desired position, as shown in FIG. 1B. Preferably, the via 10 isformed through the use of a drilling method, but any conventionalmethod, such as punching, laser drilling, or photo-definition, can beused. The via 10 can be any diameter, but is preferably in the rangebetween about 2 mils and about 25 mils. Preferably, all or substantiallyall of the openings or holes in the printed circuit board are formed atthe same time, whether they are ultimately to be filled, as describedbelow, or not. This avoids misregistration, especially from tolerancebuildups, that can occur between the filled and unfilled vias betweenthe separate hole forming processes and the subsequently formed wiringpatterns that are formed by the use of one or more masks that must beregistered with the holes. This factor is especially important as PCBwiring patterns become finer and more dense.

[0031] Thereafter, as shown in FIG. 1C, a first conductive layer 14 of afirst conductive material is deposited on the surfaces of the substrate12 and on the sidewalls 16 of the via 10 to leave a via-through-hole 11in the via 10. Preferably, the first conductive material is copper. Thefirst conductive material is preferably deposited to a thickness in therange between about 0.1 and about 0.8 mils, and more preferablydeposited to a thickness of greater than approximately 0.2 mils, andmost preferably to a thickness of approximately 0.5 mils. The layer 14on the sidewalls is preferably thick enough to provide a robustmechanical structure that will survive the thermal fluctuations andaggressive handling experienced by a PCB during subsequent componentassembly and usage.

[0032] Preferably, an electrolytic plating process is used to depositthe layer 14. The electrolytic process follows a surface preparationstep involving either a direct metallization process or an electrolessprocess. The surface preparation step includes depositing a thinconductive layer that sensitizes the surface and assists in the adhesionof the layer 14 to the sidewalls 16. It should be noted that IBM doesnot use an electrolytic plating process and thus is limited to aconductive layer thickness typical of electroless depositions, which islimited to approximately 0.2 mils. IBM does not use electrolytic platingbecause a surface preparation step involving depositing a thinconductive layer will either cover the entire pattern, thereby renderingthe device inoperable, or involve additional processing steps leading toincreased complexity and higher cost.

[0033] Direct metallization comprises depositing a thin conductivemolecular layer (not shown) on the substrate surfaces and the viasidewalls prior to depositing the layer 14. The conductive layer ispreferably palladium or platinum. This process avoids the typicalcatalytically deposited copper, thereby rendering this device moreeconomically feasible.

[0034] The electroless surface preparation process comprises depositinga thin conductive layer (not shown), preferably copper, on the substratesurfaces and the via sidewalls prior to depositing the layer 14, to athickness in the range between about 30 micro-inches and about 200micro-inches, and more preferably to a thickness in the range betweenabout 70 micro-inches and about 80 micro-inches.

[0035] The surface preparation followed by electrolytic depositionresults in a highly linear distribution of the layer 14 on the sidewalls16 of the via 10.

[0036] After the sidewalls 16 of the via 10 have been plated with thelayer 14, a second conductive material 18, such as a conductive ink,paste, or adhesive, is introduced into the via-through-hole 11 as shownin FIG. 1D. Preferably, the second conductive material 18 is aconductive ink, preferably containing silver, copper, or a noble metalsuspended in an epoxy resin, such as CB100, manufactured by E. I. duPont de Nemours and Company of Wilmington, Delaware. However, anyflowable, curable composition with conductive properties can be used asthe second conductive material. The second conductive material 18 ispatterned for deposition in the via-through-hole 11 using a stencil or amask. After the second conductive material 18 is deposited in thevia-through-hole 11, the second conductive material 18 is partially ortack cured, and any excess material 18 (usually in the form of a smallpeak or cap extending above layer 14) is removed by, for example, lightmechanical abrasion. Preferably, no conductive material 18, such as inkparticles, remains on the layer 14 after the removal process. The secondconductive material 18 is then hard cured. The second conductivematerial 18 is preferably sufficiently conductive to allow subsequentplating of a conductive cap layer over the filled and plated via 10.

[0037] After the second conductive material 18 is cured, layers 20 and22 of a third conductive material, preferably copper, are formed on bothmajor surfaces, respectively, of the insulator substrate 12 inclusive ofboth ends of the second conductive material 18, as shown in FIG. 1E.That is, the upper conductive layer 20 and the lower conductive layer 22extend across the via 10 and are in electrical communication with eachother through the second conductive material 18 and the first conductivelayer 14. Thus, the via 10 is sealed by the conductive layers 20 and 22,with the conductive layers 20 and 22 acting as a conductive cap.

[0038] The conductive layers 20 and 22 can be formed by any conventionalprocess such as attaching a copper film to the substrate or plating acopper layer on the substrate. Preferably, feature plating or panelplating is used to deposit copper to a thickness in the range betweenabout 0.4 mils and about 0.8 mils, and more preferably to a thickness ofapproximately 0.5 mils.

[0039] Thereafter, the conductive layers 14, 20 and 22 are shaped in adesired configuration to obtain desired wiring patterns, through the useof conventional photolithography and print and etch methods, foradditive circuitization and solderability.

[0040] Because the sidewalls 16 are plated with the first conductivelayer 14 prior to introducing the second conductive material 18, thereliability of the electrical connection between the upper conductivelayer 20 and the lower conductive layer 22 is increased. Moreover, thelayer 14 improves the structural integrity of the connection between theconductive layers 20 and 22 and provides a more robust structure.

[0041] In accordance with the present invention, a plurality of vias 10can be formed concurrently in the insulator substrate 12 at desiredpositions. During subsequent processing, the vias 10 are filled with theconductive material 18 at the same time, preferably using a stencil.This provides improved registration of the vias and circuit patternsformed on the substrate.

[0042] The present invention allows for the conservation and recaptureof the conductive fill material 18. Because a stencil is used to fillthe via(s), material usage of the conductive fill material is decreasedbecause the stencil captures excess conductive material 18 which can berecovered without contamination, unlike prior methods in which theexcess conductive fill material resides on a copper layer whichcontaminates the conductive fill material, thus rendering it unsuitablefor recovery and reuse. These factors are important to manufacturingcosts because curable conductive materials tend to be very expensive.Moreover, because a stencil is used to fill the via(s) 10, the presentinvention provides the advantage of being able to use a higher force onthe squeegee blade to fill the via(s) 10 with the conductive fillmaterial 18, an advantage believed to be especially useful to ensurecomplete filling of blind vias. A higher force can cause the coppersurface to scratch. A stencil protects against this damage.

[0043]FIG. 2 depicts an exemplary surface mount land 30 aligned with afilled and plated via 10 as well as a pattern 35 aligned with a filledand plated via 10.

[0044] The double sided printed wiring board described above allows thesurface mount land 30 and a pattern on the opposite side to beelectrically conductively interconnected by way of the filled and platedvia 10. This eliminates the need of providing a via remotely from thesurface mount land 30, and therefore it is not necessary to implement awiring pattern to interconnect the surface mount land 30 to a remotevia. Thus, a high density packing can be realized.

[0045] Although the above exemplary embodiments have described vias andmethods of making vias between two opposing surfaces of a circuit boardor insulator substrate, it is nevertheless intended that the exemplaryvias and methods of making vias can also be used to provide electricalcommunication between wiring patterns formed within the internalsurfaces or strata of a circuit board. Moreover, the present inventionis equally applicable to blind hole vias, i.e, vias that do not open onboth sides of a circuit board. Thus, the present invention can be usedto connect a surface of a circuit board with one of the internal strataof the board.

[0046] When introducing elements or features of the present invention orthe preferred embodiments thereof, the articles “a”, “an” “the” and“said” are intended to mean that there are one or more of such elementsor features. The terms “comprising”, “including” and “having” areintended to be inclusive and mean that there may be additional elementsor features other than those listed.

[0047] As various changes could be made in the above constructionswithout departing from the scope of the invention, it is intended thatall matter contained in the above description or shown in theaccompanying drawings shall be interpreted as illustrative and not in alimiting sense.

What is claimed:
 1. A method of preparing a printed circuit board (PCB),comprising the steps of: forming a hole in a substrate to form a viahaving a sidewall extending therethrough; depositing a first conductivematerial on opposite sides of the substrate and on the sidewall of thevia; filling the via with a second conductive material to plug the viasuch that the via has no opening extending completely therethrough in adirection generally perpendicular to the opposite sides of thesubstrate; and depositing a third conductive material on the firstconductive material and on ends of the second conductive material in thevia.
 2. The method according to claim 1, wherein the step of forming thehole comprises one of drilling the hole, punching the hole, laserdrilling the hole, and forming the hole by photo-definition.
 3. Themethod according to claim 1, wherein the first conductive materialcomprises copper.
 4. The method according to claim 3, wherein the stepof depositing the first conductive material includes electrolyticallydepositing the first conductive material to a substantially uniformthickness of greater than approximately 0.2 mils.
 5. The methodaccording to claim 4, wherein the substantially uniform thickness isapproximately 0.5 mils.
 6. The method according to claim 1, furthercomprising the step of masking the substrate with a stencil to permitselective filling of the via prior to the step of filling the via. 7.The method according to claim 1, wherein the second conductive materialis a conductive ink.
 8. The method according to claim 7, furthercomprising the step of curing the conductive ink prior to the step ofdepositing the third conductive material.
 9. The method according toclaim 8, further comprising the step of removing any of the conductiveink extending out of the via prior to the step of depositing the thirdconductive material.
 10. The method according to claim 7, wherein theconductive ink comprises at least one of silver, copper, and a noblemetal.
 11. The method according to claim 1, wherein the step ofdepositing the third conductive material comprises one of featureplating and panel plating, and the third conductive material comprisescopper.
 12. The method according to claim 11, wherein the step ofdepositing the third conductive material includes depositing the thirdconductive material to a substantially uniform thickness of betweenabout 0.4 mils and about 0.8 mils.
 13. The method according to claim 12,wherein the substantially uniform thickness is approximately 0.5 mils.14. The method according to claim 1, further comprising the step ofdepositing a fourth conductive material on the opposite sides of thesubstrate and on the sidewall of the via prior to the step of depositingthe first conductive material.
 15. The method according to claim 14,wherein the fourth conductive material comprises one of palladium andplatinum.
 16. The method according to claim 14, wherein the step ofdepositing the fourth conductive material includes depositing the fourthconductive material to a substantially uniform thickness of betweenabout 30 micro-inches and about 200 micro-inches.
 17. The methodaccording to claim 16, wherein the substantially uniform thickness isbetween about 70 micro-inches and about 80 micro-inches.
 18. The methodaccording to claim 1, wherein the substrate comprises a resin material.19. The method according to claim 18, wherein the resin material is aglass-filled resin material.
 20. The method according to claim 1,further comprising the step of etching the first and third conductivematerials so as to form wiring patterns on the opposite sides of thesubstrate.
 21. A method of making a conductive via in an insulatorcircuit board substrate adapted to carry wiring patterns on at least afirst surface and a second surface thereof, comprising the steps of:providing an insulator substrate; forming a via having a sidewall in theinsulator substrate between the first surface and the second surface bypenetrating the insulator substrate; depositing a first conductive layeron the first surface and on the sidewall of the via such that the firstconductive layer substantially covers the first surface of the insulatorsubstrate and the sidewall of the via while leaving an opening in thevia; depositing a conductive material in the opening of the via to plugthe via such that the opening does not extend completely through the viain a direction generally perpendicular to the first and second surfaces;and forming a second conductive layer on the first surface of theinsulator substrate subsequent to the forming of the via, the depositingof the first conductive layer, and the depositing of the conductivematerial in the opening such that the second conductive layer forms asubstantially flat surface extending across substantially all of thefirst conductive layer and across an end portion of the conductivematerial in the via so that the end portion is covered by and makesdirect contact with the second conductive layer.
 22. The methodaccording to claim 21, further comprising the step of etching the firstand second conductive layers so as to form a wiring pattern on the firstsurface of the insulator substrate, the wiring pattern beingelectrically connected through the via to the second surface.
 23. Themethod according to claim 21, further comprising the step of masking theinsulator substrate with a stencil to permit selective filling of theopening prior to the step of depositing the conductive material in theopening, wherein the conductive material is deposited so as tocompletely fill the opening.
 24. The method according to claim 21,wherein the step of depositing the second conductive layer comprises oneof feature plating and panel plating and the first and second conductivelayers comprise copper.
 25. The method according to claim 21, whereinthe conductive material is one of a conductive ink, a conductive paste,and a conductive adhesive.
 26. The method according to claim 21, whereinthe insulator substrate comprises a glass-filled resin material.
 27. Amethod of preparing a printed circuit board (PCB), comprising the stepsof: forming a hole on at least one side of a substrate to form a viaextending at least partially through the substrate to an internalsurface of the substrate, the via having a sidewall; depositing a firstconductive material on said one side of the substrate and on thesidewall of the via such that the via has an opening; masking thesubstrate with a stencil; filling the opening with a second conductivematerial by moving the second conductive material through an opening inthe stencil to plug the via such that the opening in the via does notextend completely through the via in a direction generally perpendicularto said one side of the substrate; and depositing a third conductivematerial on the first conductive material and on an end of the secondconductive material in the opening.
 28. The method according to claim27, wherein the step of depositing the first conductive materialcomprises electrolytically plating copper to a substantially uniformthickness exceeding approximately 0.2 mils.
 29. The method according toclaim 27, wherein the second conductive material is a conductive ink.30. A method of preparing a printed circuit board (PCB), comprising thesteps of: forming a plurality of holes on at least a first surface of asubstrate to form a plurality of vias extending at least partiallythrough the substrate to a second surface of the substrate, the viashaving sidewalls; depositing a first conductive material on at least thefirst surface of the substrate and on the sidewalls of the vias suchthat each of the vias has an associated opening; masking the substratewith a stencil to selectively cover a first predetermined number of thevias and reveal a second predetermined number of the vias; filling theopenings associated with the revealed vias with a second conductivematerial; and depositing a third conductive material on the firstconductive material and on ends of the second conductive material in thefilled openings.
 31. The method according to claim 30, wherein the stepof depositing the first conductive material comprises electrolyticallyplating copper to a substantially uniform thickness exceedingapproximately 0.2 mils.
 32. A circuit board comprising: a substratehaving at least first and second generally parallel surfaces and a viaextending through the substrate from the first surface to the secondsurface, the via having a sidewall; a first conductive layer extendingover substantially all of the first surface and the via sidewall; aconductive material positioned within the via and surrounded by thefirst conductive layer extending over the via sidewall, the conductivematerial plugging the via such that the via has no opening extendingfrom the first surface to the second surface; and a second conductivelayer extending over substantially all of the first conductive layer onthe first surface, and over an end portion of the conductive materialpositioned within the via.
 33. The circuit board of claim 32 wherein thefirst and second surfaces are exterior surfaces of the substrate. 34.The circuit board of claim 32 wherein the first conductive layercomprises copper.
 35. The circuit board of claim 34 wherein the secondconductive layer comprises copper.
 36. The circuit board of claim 32wherein the conductive material positioned within the via is selectedfrom the group consisting of conductive inks, conductive pastes, andconductive adhesives.
 37. The circuit board of claim 36 wherein theconductive material is a conductive ink.
 38. The circuit board of claim37 wherein the conductive ink comprises at least one of silver, copper,and a noble metal.
 39. The circuit board of claim 32 wherein the firstand second conductive layers are adapted to be etched to thereby formwiring patterns on either one or both of the first and second surfaces.40. The circuit board of claim 32 wherein the substrate comprises aresin material.
 41. A circuit board comprising: a substrate having atleast first and second generally parallel surfaces and a via extendingthrough the substrate from the first surface to the second surface, thevia having a sidewall; a first conductive layer extending oversubstantially all of the first surface, the second surface, and the viasidewall; a conductive material positioned within the via and surroundedby the first conductive layer extending over the via sidewall, theconductive material plugging the via such that the via has no openingextending from the first surface to the second surface; a secondconductive layer extending over substantially all of the firstconductive layer on the first surface, and over a first end portion ofthe conductive material positioned within the via; and a thirdconductive layer extending over substantially all of the firstconductive layer on the second surface, and over a second end portion ofthe conductive material positioned within the via.
 42. The circuit boardof claim 41 wherein the first and second surfaces are exterior surfacesof the substrate.
 43. The circuit board of claim 41 wherein the secondand third conductive layers each comprise copper.
 44. The circuit boardof claim 41 wherein the first, second and third conductive layers areadapted to be etched to thereby form wiring patterns on either one orboth of the first and second surfaces.
 45. The circuit board of claim 41wherein the substrate comprises a resin material.